Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> virtual platforms
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
virtual platforms
acceleration
Accellera
ARM
ARM Techcon
boot loader
C++
Cadence
Cortex-A9
Davidmann
Debug
debugging
DVCon
EDA
EDA360
edaForum
embedded software
emulation
emulator
EPP
ESL
extensibility
extensible
FAQ
fast models
fixed sub-systems
flash memory
Flash Memory Summit
Flex Channels
FPGA
FPGA prototyping
FPGA-based prototypes
FPGA-based prototyping
Frank Schirrmeister
Gary Smith
hardware/software co-development
hardware/software integration
High-level Synthesis
HLS
Imperas
Incisive
incisive software extensions
Industry Insights
Intel
IP
ip-xact
ISX
Jim Hogan
kernel
linux
Memory
models
multi-core
NASCUG
OSCI
OVP
Palladium
Palladium XP
power
prototyping
Qualcomm
rapid prototyping
Reference Flow 12
RTL
Schirrmeister
Simulation
software
system design
System Design & Verification
System Design and Verification
System Design and Verification
System Development Suite
system level
system realization
SystemC
system-level
System-Level Design
TLM
TLM 2.0
TLM2
TLM-2.0
TSMC
UART
Ubuntu
verification
Verification Computing Platform
video
VIP
Virtual
Virtual Machine
virtual prototoypes
virtual prototoyping
virtual prototype
virtual prototypes
Virtual System Platform
VirtualBox
VSP
Xilinx
zynq
Zynq-7000
Zynq-7000'
Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform
There are two choices for how to handle USB devices in a virtual platform. A USB device can be modeled using C/C++ programming, or a physical USB device can be plugged into a computer and attached to the simulator. The Xilinx QEMU for Zynq uses physical USB devices. The Cadence SystemC Virtual Platform...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Thu, May 24 2012
In-Circuit Acceleration – A New IC Verification Use Model
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 15 2012
American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working On!
I think all of us engineers have faced at one point or another the need to explain to our parents or friends what we are actually working on. Hey Mom, EDA is where electronics begins! Without us electronics would not change our day to day lives ... Punctually for Mothers day, which I spent with my Mom...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, May 14 2012
Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox
In my last blog post , I covered three frequently asked questions about using the Xilinx Zynq-7000 Virtual Platform as a VirtualBox appliance. Today, I'll cover the next most frequently asked question. It is related to simulation performance. This should not be considered an official benchmark as...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Mon, May 7 2012
Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition
The use of virtual machine technology offers great ease of use benefits. Since the virtual platform for the Xilinx Zynq-7000 Extensible Processing Platform has been available as a virtual machine appliance, I have seen it run by many people who would probably not be able to install and configure a traditional...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Wed, May 2 2012
Is System Modeling the Next EDA Abstraction Level?
According to a recent talk by Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, the answer is "yes." System modeling is a level of abstraction that's independent from hardware and software implementation. But there are some interesting...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 15 2012
Modeling Large Memories in SystemC
Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded systems have a gigabyte or more of SDRAM. For example, one of the Xilinx Zynq boards, known as ZC702, has a Linux Device Tree source file defining the memory size as 0x40000000, or 1 Gb. Thinking about a SystemC model...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Apr 13 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 7 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems
The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Thu, Feb 23 2012
The Zynq Virtual Platform: Not Just for Pre-Silicon
One of the biggest misconceptions about Virtual Platforms is that they are only useful for pre-silicon software development, and once a chip and board is ready they are quickly discarded. Even after boards are available, Virtual Platforms are valuable for software development. Last week I was talking...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Tue, Feb 7 2012
Page 1 of 5 (48 items) 1
2
3
4
5
Next >