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video,uvm

Free UVM Tutorial Boosts IC Functional Verification Skills

Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 12 2012
Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study With the GoPro Hero2 Camera

Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses. Clearly both sides of the low power coin -- reducing generated heat and/or increasing efficiency to make the...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Sep 12 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos . The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 23 2012
UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action . It is a must see for the cowbell aficionado. Coincidentally...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 16 2012
My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647) Initially I thought: "What is the fuss all about?" While exploring the language during the development of the cowbell videos , it hit me -- I started to recognize the power of Aspect Oriented...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Jul 10 2012
DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional Verification

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK , teaches a course on functional verification. In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped...

Posted to Functional Verification (Weblog) by jvh3 on Thu, Jul 5 2012
Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed

In the world of Star Trek " resistance is futile " when you encounter the Borg . Fortunately, in verification we do not have to deal with the Borg. Nonetheless, our world provides plenty of challenges. Schedules are tight, problems are complex, and market windows are narrow. In other words...

Posted to Functional Verification (Weblog) by Axel Scherer on Fri, Jun 1 2012
Get Started on UVM-e with Free Introductory Video Tutorials

One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...

Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012

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video,uvm

Free UVM Tutorial Boosts IC Functional Verification Skills

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study With the GoPro Hero2 Camera

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional Verification

Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed

Get Started on UVM-e with Free Introductory Video Tutorials