Home > Community > Tags > vias
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • How delete a routed Net completely

    Hi, I want to delete a routed net completely. I have made appropriate options in find filter ON - Vias & Clines & Nets - and selected them in Delete Net Options as well. As depicted below net is selected whenever I click on it but it is not deleted. I receive below message: No element found....
    Posted to PCB Design (Forum) by Hossein1357 on Sun, Aug 10 2014
  • Binary Data Bus via programming script

    Is there a simple, automated way of placing vias from a data bus in a binary pattern to instances like decoders?
    Posted to Custom IC SKILL (Forum) by jaleco on Mon, Jul 21 2014
  • Customer Support Recommended - Implementing Jumpers in Allegro PCB Editor

    Over the time, jumpers have found their importance in multiple applications . The following blog is aimed to provide more insight on their usage and implementation using Cadence Allegro PCB Editor . What is a jumper? A wire jumper is typically a short wire used to electrically connect two points. On...
    Posted to PCB Design (Weblog) by Naveen on Tue, Jan 7 2014
  • Why the same net via and shape can not connect togeter?

    I have met a problem when use 16.5 in divide power layer, the same net with the dynamic shape and via cannot connect together. just like pic as follow or link. The via avoid the shape. And I want to know how to solve it, thanks a lot! http://xiangce.baidu.com/picture/detail/8f2f80782f2eeecf44752e05fa10543a59b5931c
    Posted to PCB Design (Forum) by Sunner on Fri, Nov 22 2013
  • What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!

    A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within the cline path, pins, shapes, and flow lines. Useful in just about any PCB application, the display of net names will be extremely valuable for those involved in design reviews or board debug. This feature is enabled...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Oct 15 2013
  • How to connect vias to specific layers

    I have a design which has 7 layers. The top layer has only short stubs. There are two layers for traces but they are sensitive signals and there is a solid ground plane above and below these two layers. I have connected these two planes at one point near the incoming supply. I also have a single ground...
    Posted to PCB Design (Forum) by tmd63 on Thu, Sep 26 2013
  • Using Skill to Select Vias not fully enclosed by metal

    Is there a way to only select vias that cross a shape boundry? I have a very large FET that has numerous Source and Drain Vias and the top level metal covering them now has to be slotted leaving a large amount of existing Vias to be manually deleted where the slots pass over them. I can generate another...
    Posted to Custom IC SKILL (Forum) by Terry S on Mon, Aug 12 2013
  • What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New Enhancements!

    The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that exports to ADS, and also the enhancements for existing layout IFF interface (import and export) to support...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Jun 11 2013
  • Forcing via connections

    I have a multi-layer design with multiple ground plane layers. But these have issues with ground loops. How can I set something in PCB Editor 16.5 that will only connect vias to one ground plane layer and leave all other layers unconnected, so that I can use a single ground connection point.
    Posted to PCB Design (Forum) by tmd63 on Fri, May 3 2013
  • How do I create a stack of vias

    We sometimes need to define a thruhole via as a stack up of blind microvias and buried vias. This is becasue on th eTop and Bottom layers I need a smaller pad, that cannot be acieved with thruhole via, but only with blind micorvias. Is it possible in PCB Editor to define such a via, or at least to place...
    Posted to PCB Design (Forum) by Leticia on Fri, Apr 5 2013
Page 1 of 3 (22 items) 1 2 3 Next >