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via
"PCB design"
"SoC-Encounter"
16
16.2
2.5D
28nm
3D
3D IC
3D-IC
Add Via
Allegro
Allegro 16.3
Allegro 16.5
Allegro PCb
Allegro PCB Editor
Allegro PCB SI
blind vias
Brian Wallace
buried vias
Cline change
Constraint Manager
dbcreatevia
design
DFM
diff pairs
Differential Pair Support
differential pairs
digital
Digital Implementation
Drill holes
EDI
EDI 11
EDI 11.1
EDI system
encounter
extracta
Footprint
formulas
foundry
Gerber
global route
grids
group routing
GSA
GSA 3D IC
HDI
High Speed
High-Density Interconnect
highlighting
Industry Insights
inset vias
interconnects
Ken Potts
layer stacks
layout
LMB
microvia
miniaturization
multi-cut via insertion
NanoRoute
orcad layout plus
OSAT
PCB
PCB Capture
PCB design
PCB Editor
PCB Layout and routing
Potts
power density
routing
Si2
SiP
skill
Skill Code
SoC-Encounter
SPB
SPB 16.2
SPB 16.3
SPB16.3
SPB16.5
Specctra
stacked die
staggered vias
standard via
Standards
thermal relief
thernal
TSV
via patterns
via rules
via skill dbcreatevia
via tangency
vias
Virtuoso 6.1.5
wide i/o
wide io
Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 21 2012
What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements!
More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available in the 16.5 release of the Allegro PCB Router...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, May 8 2012
What's Good About Allegro Via Patterns During Group Routing? See for Yourself in 16.5!
New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns during group routing. Group Routing Review The Allegro PCB Editor supports interactive group routing. Interactive group routing is the routing of more than one net concurrently. You can use this feature when routing...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Mon, Apr 30 2012
When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows
Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings...
Posted to
Digital Implementation
(Weblog)
by
wally1
on Thu, Apr 5 2012
In which file does the Vias widths and heights will be present
In SoC encounter, after loading my floorplan, i 'm checking out vias dimensions (widht and height) individually through attribute editor. In what format, does this information stored under fp file or another file.
Posted to
Digital Implementation
(Forum)
by
kranthiskype
on Wed, Apr 4 2012
What's Good About Allegro PCB Router Inset Vias? See for yourself in 16.5!
Another high density interconnect (HDI) technology that has gained popularity is inset vias. The 16.5 release has provided new commands added in Allegro PCB Router to support inset vias. Via in Pad pattern has been very popular due to its clear advantage of offering lower parasitics as compared to other...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Jan 10 2012
Re: dbCreateVia() questions: justification and other examples
I never found or was given a clean solution. I wrote some bimodal code to consistently place a contact in either IC5.1 or IC6.1, like below. HTH, Trevor procedure(apcCreateContact(@key ;_Oct 7 11 tbowen 528 cv master origin rotation width height rows columns xPitch yPitch xBias yBias viaEdgeCenter )...
Posted to
Custom IC SKILL
(Forum)
by
TrevorB
on Thu, Nov 3 2011
dbCreateVia() questions: default versus override params
I am building a procedure using the parameters of the object Via. I am changing the overrideParams of concern in order to increase or decrease the parameter value. The issue I have and I am not understanding is that when I am arriving to the default value of the parameter after decrease the value with...
Posted to
Custom IC SKILL
(Forum)
by
frogconsultant
on Thu, Nov 3 2011
What's Good About Allegro PCB Router HDI Via Tangency? Check Out 16.5!
High Density Interconnect (HDI) techniques are increasing in the PCB domain. HDI provides the ability to place components on both sides of the board and helps reduce the PCB layer stack. Allegro PCB Router started evolving in this direction from the SPB16.2 version with drill holes and microvias. In...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Wed, Oct 5 2011
Re: Error in addvia code
Hello Andrew Thanks for looking into the code. I reran the script after making the changes suggested by you. However, now the vias placed by calling the addVia() function retain the values of the last placed via. For e.g. if a TV was placed before placing a Via2/Via3, then the via2/via3 would be placed...
Posted to
Custom IC SKILL
(Forum)
by
brittooo
on Mon, Sep 12 2011
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