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via
"PCB design"
"PCB SI"
"SoC-Encounter"
16
16.2
16.3
16.5
16.6
2.5D
28nm
3D
3D IC
3D-IC
Add Via
advanced package designer
allegro
Allegro 16.3
Allegro 16.5
Allegro 16.6
Allegro GUI
Allegro Package Designer
Allegro PCb
Allegro PCB Editor
Allegro PCB SI
APD
blind vias
Brian Wallace
buried vias
Cadence
Cadence SKILL
change net
change property
Cline change
Constraint Manager
create via
dbcreatevia
dbGet
dbReplacePropList dbReplaceProp list documentation pcell
design
Design Reuse
DFM
diff pairs
Differential Pair Support
Differential pairs
digital
Digital Implementation
Digital SiP design
Drill holes
ecounter
EDI
EDI 11
EDI 11.1
Gerber
global route
Grzenia
HDI
High Speed
High-Density Interconnect
inset vias
interconnects
layer stacks
layout
microvia
NanoRoute
orcad layout plus
OSAT
packaging
padstack
PCB
PCB Capture
PCB design
PCB Editor
PCB Layout and routing
PCB SI
PCB Signal and power integrity
PCB Signal integrity
PCB Stackup
routing
Si2
signal integrity
Signal Intregrity
skill
SPB
SPB 16.2
SPB 16.3
SPB16.3
SPB16.5
Specctra
stacked die
stacked vias
via patterns
via rules
via skill dbcreatevia
via stack-up
via tangency
ViaCell
vias
Virtuoso 6.1.5
wide i/o
wide io
Forcing via connections
I have a multi-layer design with multiple ground plane layers. But these have issues with ground loops. How can I set something in PCB Editor 16.5 that will only connect vias to one ground plane layer and leave all other layers unconnected, so that I can use a single ground connection point.
Posted to
PCB Design
(Forum)
by
tmd63
on Fri, May 3 2013
How do I create a stack of vias
We sometimes need to define a thruhole via as a stack up of blind microvias and buried vias. This is becasue on th eTop and Bottom layers I need a smaller pad, that cannot be acieved with thruhole via, but only with blind micorvias. Is it possible in PCB Editor to define such a via, or at least to place...
Posted to
PCB Design
(Forum)
by
Leticia
on Fri, Apr 5 2013
How to assign/update an etch objects' net
Unaware I was in the wrong forum, I've been posting this PCB layout question in the Digital Implementation forum http://www.cadence.com/Community/forums/p/23378/1322026.aspx#1322026 I am trying to take a group of pre-selected vias and change the net that they are on. My inquiry is as follows: Apparently...
Posted to
PCB Design
(Forum)
by
RaylonS
on Thu, Mar 28 2013
What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements!
In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models. Read on for more details … Adding Vias Adding a via is easier and faster than before. You no longer have to...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Mon, Mar 25 2013
update "cutSpacing" of a via
Hi guys, Long time lurker, first time poster. I first want to thank Andrew, Lawrence and other regulars for contributing to this forum. I have a simple problem that I can't seem to figure out and I am hoping you guys can point me to the right direction. I am trying to update the "cutSpacing"...
Posted to
Custom IC SKILL
(Forum)
by
chianga
on Tue, Dec 18 2012
What's Good About APD’s Shape Shorting? You’ll Need the 16.6 Release to See!
In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Nov 13 2012
What is the best way to create a GSSG differential via structure?
I would like to use GSSG differential via structure for the 10G Serdes signal routing. What is the best way to implement GSSG differential via structure? How to make a oblong shape Anti pad for the two differential vias? Look forward to your help. Thanks.
Posted to
PCB Design
(Forum)
by
Xu Zhou
on Thu, Oct 25 2012
How to assign VIA to a net name?
Hello, I'm having problems with adding/naming Vias. I select the "Add via", then "by geometry", specify it's geometry and put (click) it over an existing net. The problem however is, that the Via isn't connected to the net. The attribute window says it's net is _NULL...
Posted to
Digital Implementation
(Forum)
by
mizzihood
on Fri, Aug 17 2012
Error: Padstacks missing thermal/antipad definitions?
Hey everyone, Background: I am new to Cadence, and am going through a simple tutorial on how to create a 555 LED blinker circuit using the Cadence suite. Following the tutorial, I drew the schematic in OrCAD, created a few custom pads and footprints, placed the components in Allegro, and autorouted the...
Posted to
PCB Design
(Forum)
by
bnaden
on Thu, Jun 7 2012
Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 21 2012
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