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  • via size

    when I try to add via with this command: editPowerVia -add_vias 1 -via_rows 3 -via_columns 1 -top_layer M8 -bottom_layer M5 -orthogonal_only 1, it shows following warning and vias are not added. **WARN: AddVia Warning: can't specify cut numbers for stack vias **WARN: AddVia: please specify via size...
    Posted to Digital Implementation (Forum) by iullah on Wed, Apr 2 2014
  • Re: Connecting plated mounting holes to Planes

    Thanks, the holes are not electrical symbols. They are mechnical symbols (MTG156) that I placed from the machanical parts list under the "place manually" menu.
    Posted to PCB Design (Forum) by fvascon on Fri, Oct 4 2013
  • How do I count the number of holes and vias on a board?

    I am trying to get a quote for a board and the manufacturer needs to know the number of holes there will be. Is there a quick and easy way to count how many I have on my board with Allegro? For example, is there a way to find how many instances of vias there are? Thanks in advance!
    Posted to PCB Design (Forum) by Oscilliscoper on Thu, Aug 8 2013
  • How to Add Specially Created Via Padstacks to Just the Design Database vs. Library?

    For a design, trying to keep some specially created via padstacks out of the general library path and instead just keep with the design database. In the Allegro Constraint Manager, there are two options for assigning vias to the nets but it's not clear how to get these new, specially-created via...
    Posted to PCB Design (Forum) by RMS707 on Mon, Jul 22 2013
  • What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New Enhancements!

    The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that exports to ADS, and also the enhancements for existing layout IFF interface (import and export) to support...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Jun 11 2013
  • Re: How do you control what layer a via connects to?

    In the constraint manager, would I go to Physical > Net > All Layers and then set it for the wire I'm interested in under the "Via" column?
    Posted to PCB Design (Forum) by Oscilliscoper on Mon, Jun 10 2013
  • How do you control what layer a via connects to?

    Another very basic and stupid question, I'm sure: How do I control what layer a via is connected to? I know that when laying down wires, you have to double click to make a via, but that makes a via from the top layer to the bottom layer or vice versa. How can I change the via to be from layer x to...
    Posted to PCB Design (Forum) by Oscilliscoper on Sun, Jun 9 2013
  • Power Stripe - Power Via Generation in Encounter

    I am trying to use a power ring, special routing, and power stripes for my power routing. I can set up the ring, special routing, and stripes correctly as far as location is concerned. However, I am having spacing violations in Encounter (and after exporting to Cadence using oaout) where it places power...
    Posted to Digital Implementation (Forum) by bsparkma on Wed, May 22 2013
  • Forcing via connections

    I have a multi-layer design with multiple ground plane layers. But these have issues with ground loops. How can I set something in PCB Editor 16.5 that will only connect vias to one ground plane layer and leave all other layers unconnected, so that I can use a single ground connection point.
    Posted to PCB Design (Forum) by tmd63 on Fri, May 3 2013
  • How do I create a stack of vias

    We sometimes need to define a thruhole via as a stack up of blind microvias and buried vias. This is becasue on th eTop and Bottom layers I need a smaller pad, that cannot be acieved with thruhole via, but only with blind micorvias. Is it possible in PCB Editor to define such a via, or at least to place...
    Posted to PCB Design (Forum) by Leticia on Fri, Apr 5 2013
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