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veriloga,veriloga spectre

  • Specify a file path as a parameter type in Cadence VerilogAMS

    Hello, I am writing a verilogams module to be used in my spectre sims. When this module is instantiated in my schematic, it needs to take in a path to a pwl file as a parameter input to the verilogams instance and then incorporate this filename as the file type for the "vsource" instance defined...
    Posted to Custom IC Design (Forum) by uzzy on Tue, Oct 2 2012
  • segment error for symbol

    Hello, I wrote a veriloga code for some behavioural modeling. It compiled fine and let me create a symbol. I then instantiated the symbol and tried to sim it with spectre. The spectre simulation bombs and the error message is like "segment error for symbol: pin_name" and it is referring to...
    Posted to Custom IC Design (Forum) by uzzy on Fri, Aug 3 2012
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