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veriloga,timestep control

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  • Re: Regarding Smoothness in transient analysis

    Hi RFStuff, The simulator will only place timesteps that are sufficient to resolve the equations, not necessarily enough that the sine wave looks like a sine wave. One way to help the simulator take more timesteps is to use the bound_step() function - this should be a little nicer to the simulator (than...
    Posted to Custom IC Design (Forum) by skillUser on Wed, Sep 18 2013
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