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  • Annotate veriloga or verilogams value on symbol

    Hi, I am interested in creating a symbol in Cadence which will have a label on it which is the value of a variable inside the verilog-a code of that block after a simulation has run. For instance, I have a "real" ron and I would like it's dc value to appear on my symbol. Thank you! Aaron
    Posted to Custom IC SKILL (Forum) by acook on Wed, Jul 10 2013
  • Need to place a pin on the symbol for an internal VerilogA signal

    I have an internal signal in my VerilogA code that is passed to another module, and it is not on this module's port list. But when netlisting, it complains that it wants a pin on the symbol for that signal. So my temporary solution is just to place it on the symbol and then as a no-connect on a schematic...
    Posted to Custom IC Design (Forum) by boast on Tue, May 7 2013
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