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veriloga,simulation

  • Mixed-Signal Simulation Speed Optimization

    After spending some time to setup a mixed-signal simulation, I reached a point where I can no longer increase the simulation speed. The chip core is referencing behavioral VHDL and a majority of the analog modules are represented by Verilog-A code. I am simulating using irun. I was wondering it if would...
    Posted to Custom IC Design (Forum) by TjaartOpperman on Tue, Jul 17 2012
  • Check signal value in order to stop simulation

    Hi Everyone, I am trying to optimize the simulation time but checking the value of an analog signal in the simulation. I am wondering if there is already a block (veriloga) or a function under cadence which check the value of an analog signal (i.e. for example after 10 values with 1us apart under 5%...
    Posted to Custom IC Design (Forum) by frogconsultant on Mon, Feb 14 2011
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