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  • VerilogA parsing problem

    When I check and save a verilogA file from cadence library, cadence always checks the syntax of the VerilogA file. But now if I do it, I got the following error WARNING : There is some issue in invoking spectre command for parsing the text file <path to verilogA file> Make sure that the setting...
    Posted to Custom IC Design (Forum) by StanleyN on Thu, Sep 27 2012
  • segment error for symbol

    Hello, I wrote a veriloga code for some behavioural modeling. It compiled fine and let me create a symbol. I then instantiated the symbol and tried to sim it with spectre. The spectre simulation bombs and the error message is like "segment error for symbol: pin_name" and it is referring to...
    Posted to Custom IC Design (Forum) by uzzy on Fri, Aug 3 2012
  • Mixed-Signal Simulation Speed Optimization

    After spending some time to setup a mixed-signal simulation, I reached a point where I can no longer increase the simulation speed. The chip core is referencing behavioral VHDL and a majority of the analog modules are represented by Verilog-A code. I am simulating using irun. I was wondering it if would...
    Posted to Custom IC Design (Forum) by TjaartOpperman on Tue, Jul 17 2012
  • BSIM4 cadence implementation

    Hi everyone. Is BSIM4 model implemented in cadence is anyhow different from the official one specified by BSIM group? This derives from comparing a verilog-a model released from another company also implementing BSIM4 also against the cadence one and the results are somehow different. For example parameters...
    Posted to Custom IC Design (Forum) by soathana on Wed, Jul 4 2012
  • verilog-a - model ac biasing

    Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre. kind regards, Sotiris
    Posted to Custom IC Design (Forum) by soathana on Thu, May 10 2012
  • Beginner questions: Verilog-a - Custom Models

    Hi everybody, I am creating a custom transtistor model with verilog-a and using it at a symbol with ADE and I have some questions: 1)Is there a dedicated way to parse verilog code? so far the thing I have been doing is editing the code inside its cell and then when I close it after a while verilog parser...
    Posted to Custom IC Design (Forum) by soathana on Tue, Apr 17 2012
  • Check signal value in order to stop simulation

    Hi Everyone, I am trying to optimize the simulation time but checking the value of an analog signal in the simulation. I am wondering if there is already a block (veriloga) or a function under cadence which check the value of an analog signal (i.e. for example after 10 values with 1us apart under 5%...
    Posted to Custom IC Design (Forum) by frogconsultant on Mon, Feb 14 2011
  • Stop Simulation by Itself

    Is there a way to stop a simulation after a certain condition have been met? - ( VerilogA maybe? ) Example: I setup a transient simulation to run for 50m secons. The circuit oscillates for an unknown frequency, can be too high or too low. In an alter, when the frequency is too high, the simulation time...
    Posted to Custom IC SKILL (Forum) by gilberts on Tue, Oct 13 2009
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