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veriloga,compact models

  • BSIM4 cadence implementation

    Hi everyone. Is BSIM4 model implemented in cadence is anyhow different from the official one specified by BSIM group? This derives from comparing a verilog-a model released from another company also implementing BSIM4 also against the cadence one and the results are somehow different. For example parameters...
    Posted to Custom IC Design (Forum) by soathana on Wed, Jul 4 2012
  • verilog-a - model ac biasing

    Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre. kind regards, Sotiris
    Posted to Custom IC Design (Forum) by soathana on Thu, May 10 2012
  • Beginner questions: Verilog-a - Custom Models

    Hi everybody, I am creating a custom transtistor model with verilog-a and using it at a symbol with ADE and I have some questions: 1)Is there a dedicated way to parse verilog code? so far the thing I have been doing is editing the code inside its cell and then when I close it after a while verilog parser...
    Posted to Custom IC Design (Forum) by soathana on Tue, Apr 17 2012
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