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veriloga,ac biasing

  • Re: Problem in Cadence Virtuoso AC analysis

    Hi Andrew, I had a little doubt on what parameters are explicitly needed for ac analysis. This is because I am using verilog -A based models and hence want to be sure if I am doing the right thing. As far as I know, AC analysis first computes the DC operating point: so I must define current at each operating...
    Posted to Custom IC Design (Forum) by OneNewBoy on Mon, Mar 25 2013
  • verilog-a - model ac biasing

    Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre. kind regards, Sotiris
    Posted to Custom IC Design (Forum) by soathana on Thu, May 10 2012
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