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veriloga cadence virtuoso 6.1.3 ADEL

  • Re: model card vith a verilogA model through spectre

    Hello, In my case I am declaring new quantities (nature and discipline) in my veriloga file. I needed this to boost the value of the blowup in order to avoid some convergence problems I encountered. Now, I target to set my model card. using the lines : `include "disciplines.vams" //(* compact_module...
    Posted to Custom IC Design (Forum) by kjabeur on Wed, Jul 24 2013
  • veriloga model not being found

    Hi, I'm trying to instantiate this veriloga FET model http://ptm.asu.edu/postsi.html and i followed the instructions in the pdf to instantiate as a symbol. now when i try to run a simulation, I see the error: ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'veriloga...
    Posted to Custom IC Design (Forum) by kristen on Fri, Oct 5 2012
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