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veriloga ahdl cadence virtuoso

  • Noise sources in PSS analysis

    Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...
    Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
  • Specify a file path as a parameter type in Cadence VerilogAMS

    Hello, I am writing a verilogams module to be used in my spectre sims. When this module is instantiated in my schematic, it needs to take in a path to a pwl file as a parameter input to the verilogams instance and then incorporate this filename as the file type for the "vsource" instance defined...
    Posted to Custom IC Design (Forum) by uzzy on Tue, Oct 2 2012
  • segment error for symbol

    Hello, I wrote a veriloga code for some behavioural modeling. It compiled fine and let me create a symbol. I then instantiated the symbol and tried to sim it with spectre. The spectre simulation bombs and the error message is like "segment error for symbol: pin_name" and it is referring to...
    Posted to Custom IC Design (Forum) by uzzy on Fri, Aug 3 2012
  • Verilog-a function local variables Visualization & Analysis

    Is there a nice way to expose function variables to Visualization & analysis XL? Variables at model level can be saved with saveahdlvars option and accesible through signal browser, but not the same applies for analog function variables inside the model. Since there are a lot of them i cannot return...
    Posted to Custom IC Design (Forum) by soathana on Thu, May 31 2012
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