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verilogA ahdl cadence virtuoso ADE gcc compile mmsim,veriloga

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  • VerilogA parsing problem

    When I check and save a verilogA file from cadence library, cadence always checks the syntax of the VerilogA file. But now if I do it, I got the following error WARNING : There is some issue in invoking spectre command for parsing the text file <path to verilogA file> Make sure that the setting...
    Posted to Custom IC Design (Forum) by StanleyN on Thu, Sep 27 2012
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