Home > Community > Tags > verification/e/eVC
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

verification,e,eVC

  • end-of-test

    Hi All, I am running one testcase in which i am waiting for power-on-reset to be over and then doing some sequence. In the pre_body i have raised objection and in post_body i have dropped the objection. ISSUE : In the testcase as soon as reset is getting over in the next clock edge i am getting this...
    Posted to Functional Verification (Forum) by Ravisinha on Tue, Oct 19 2010
  • test to write and read registers with field order like packing.low

    Hi, Please, tell me how to test registers when the filed order of a register is packing.low, from a low bit position to a high bit position. I applied the following code by referencing the document 'The Register and Memorr Model', but I could not get correct result. extend MY_REG vr_ad_reg_file...
    Posted to Functional Verification (Forum) by mkyang on Thu, Aug 27 2009
  • The OVM extended to support e and SystemC

    In case you missed the press release, the Open Verification Methodology (OVM) has been updated to support e as well as SystemC: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=022309_extended_ovm The first implementation of OVM was for SystemVerilog back in 2007. This donation...
    Posted to Functional Verification (Forum) by mstellfox on Wed, Feb 25 2009
Page 1 of 1 (3 items)