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Using Flexible Specman License Searches
Until recently, Specman used to look for its licenses in the following strict, hardcoded order: Either 1. "Incisive Specman Elite" 2. "Incisive Enterprise Simulator" 3. "Incisive Enterprise Verifier" Or 1. "Incisive Enterprise Simulator" 2. "Incisive Enterprise...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Jul 9 2012
Tips on Writing Macros in Specman e Language
In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following simple example. Assume that you want to define a...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, May 22 2012
The Facts: Why Accelerated VIP Is Needed for SoC Verification
On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...
Posted to
Functional Verification
(Weblog)
by
PeteHeller
on Tue, May 15 2012
Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)
Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee. Unfortunately...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, May 11 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!
The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger can handle various other problems, such as user errors, performance problems and unexpected generation...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 24 2012
“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 17 2012
Technical Tip on How to Use HDL Assertions in e
While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage. ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification. HDL assertions...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Sep 28 2011
Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API
Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting e RM, OVM, and now the full production UVM. At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Jun 22 2011
Achieve the Next Level of Verification Productivity with Specman Advanced Option
Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jan 18 2011
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