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verification

  • The OVM extended to support e and SystemC

    In case you missed the press release, the Open Verification Methodology (OVM) has been updated to support e as well as SystemC: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=022309_extended_ovm The first implementation of OVM was for SystemVerilog back in 2007. This donation...
    Posted to Functional Verification (Forum) by mstellfox on Wed, Feb 25 2009
  • top level verification plan - what's the big deal?

    Putting together a solid top level verification plan is not an easy task... It's actually quite different from writing a verification plan for a standalone unit. Still, there are some basic guidelines that should be taken into consideration during the process. In the following article I tried to...
    Posted to Functional Verification (Forum) by ThinkVer on Tue, Feb 10 2009
  • Demo: Power Shut-Off (PSO) Verification in Incisive

    With more and more designs employing low power design techniques, the need to accurately verify these low power structures is critical. Unfortunately, the complexity associated with low power design often increases the complexity of low power verification. The good news is that the Incisive Unified Simulator...
    Posted to Logic Design (Weblog) by Mickey on Wed, Oct 29 2008
  • Embedded Systems Conference Boston 2008

    Friday is that last day to get the Early Bird price for the Embedded Systems Conference scheduled for October 28-30 at the Hynes Convention Center in Boston. There are a lot of great sessions on embedded software development including a track on Debugging, Verification, and Test that will be anchored...
    Posted to System Design and Verification (Weblog) by jasona on Thu, Aug 21 2008
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