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Tips on Writing Macros in Specman e Language
In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following simple example. Assume that you want to define a...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, May 22 2012
UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!
A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Mon, May 21 2012
The Facts: Why Accelerated VIP Is Needed for SoC Verification
On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...
Posted to
Functional Verification
(Weblog)
by
PeteHeller
on Tue, May 15 2012
In-Circuit Acceleration – A New IC Verification Use Model
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 15 2012
Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)
Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee. Unfortunately...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, May 11 2012
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"
To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Thu, May 3 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!
The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger can handle various other problems, such as user errors, performance problems and unexpected generation...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 24 2012
CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification
With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance...
Posted to
Mixed-Signal Design
(Weblog)
by
AElzeftawi
on Mon, Apr 9 2012
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