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DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 30 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...
Posted to
Industry Insights
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by
rgoering
on Sun, Jan 22 2012
SystemC Debug: A Summary of Summary Probes
SystemC goes well beyond generic C and C++ to provide a number of semantic constructs that are essential for system-level modeling, design and verification. Among the most powerful of these are threading and concurrency. Using threading is required in order to represent concurrent systems, whether for...
Posted to
System Design and Verification
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by
TeamESL
on Fri, May 15 2009
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