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verification,SystemVerilog,sva

  • DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

    In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
  • Webinar Seeks to “End the Debate” – e or SystemVerilog?

    Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 21 2011
  • SimVision Assertions

    I have an assertion along the lines of : assert property( @(posedge clk) A |-> B ); When I run this on Cadence, I get that the assertion failed. Looking at the waveform (counter example), it shows that when A occurs on the negedge of the clock, Cadence is still checking to see if B happened. And when...
    Posted to Functional Verification (Forum) by pdar on Fri, Jul 29 2011
  • Q&A: Zocalo President Outlines Path to Assertion-Based Verification

    It's time to move from the ad-hoc use of simple assertions to a comprehensive assertion-based methodology, according to Howard Martin, president of verification startup Zocalo Tech . This Cadence Connections partner recently released a tool called Zazz that aims to ease that transition. Zazz, which...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 9 2010
  • Async signal assetions

    Hi, There is one async signal a_sync, this signal needs to be stable till first incoming clk. a_sync signal may get change any time irrespective to clk. I have written property as follows, it works fine for single bit, but for multibit a_sync signal I need help. property abc(a_sync, clk); int temp_val;...
    Posted to Functional Verification (Forum) by SVA1 on Mon, Aug 3 2009
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