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Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 8 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models
As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 17 2012
High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump Era?
Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis Deployment: Are We Ready?," which can be found here . His conclusion is that we are getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 26 2012
DAC 2012: High-Level Synthesis Tutorial Standing Room Only
Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing SystemC to Layout , led by Michael Bohm of Intel. The first session had over 100 attendees, standing room only: Later sessions each had over 50 attendees. The tutorial featured topics ranging from designing using...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 5 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jan 22 2012
Five Modeling Abstraction Levels Clarify Meaning of “ESL”
Since I've complained in the past that electronic system level (ESL) means little more than "anything above RTL," anything that can provide more insight into just what is above RTL is welcome. I have found some clarification through five levels of modeling abstraction described in TLM-Driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 30 2010
Why Virtual Platforms Need Advanced Verification
By allowing software development long before silicon is available, virtual platforms (also known as "virtual prototypes" or simply "simulation") are playing an increasingly important role in electronic system development. But they're just an initial step in the next generation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 23 2010
Imperas Interview: Connecting Virtual Platforms To HW/SW Verification
Imperas is a provider of virtual platform technology and a member of the new Cadence System Realization Alliance . Imperas has also been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions . Simon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 12 2010
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