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DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
Free UVM Tutorial Boosts IC Functional Verification Skills
Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 12 2012
DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards
How will EDA standards move forward, now that the Accellera standards organization and the Open SystemC Initiative (OSCI) have merged into the Accellera Systems Initiative ? That was the topic of a "town hall" forum lunch at the DVCon conference Feb. 27, 2012. No presentations here, no speeches...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 27 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems
The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Thu, Feb 23 2012
DVCon Wrap-Up and Blog Review
The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 10 2011
TLM 2.0, UVM 1.0 and Functional Verification
The DVCon 2011 conference was held this week and the Accellera Universal Verification Methodology (UVM) 1.0 release is breaking records in term of interest and attendance. UVM 1.0 is a big deal(!) The core functionality is solid and ready for deployment. Accellera held a full day tutorial on UVM 1.0...
Posted to
Functional Verification
(Weblog)
by
Sharon
on Mon, Mar 7 2011
Challenging Misconceptions About Verification Languages
One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way of looking at HVLs: "Apples Versus Apples HVL...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 10 2010
DVCon Panel: Three Ways To Minimize Verification Effort
With verification taking up more and more of the design cycle, is there any hope that verification will keep up with escalating design complexity? Yes, according to panelists at the DVCon conference Thursday Feb. 25. From the discussion, I distilled three basic approaches to improving verification productivity...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 2 2010
DVCon SystemC Day – Forging A TLM Design/Verification Flow
Advanced design technologies are of no value unless there's a coherent, workable methodology that supports them. SystemC transaction-level modeling (TLM) has lacked a methodology that goes all the way to silicon without major gaps. Independent verification consultant Brian Bailey filled in some of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 23 2010
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