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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 13 2013
Develop for Debugability – Part 1
Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Apr 8 2013
Inserting electrical to real connect modules automatically
This is based on the article in EE times http://www.eetimes.com/design/eda-design/4229801/Assertion-based-verification-in-mixed-signal-design vy 2 Cadence authors. Another post similar to this used a VAMS test bench it seems http://www.cadence.com/community/forums/T/22576.aspx . I am trying to implement...
Posted to
Mixed-Signal Design
(Forum)
by
abdulahadk
on Wed, Mar 27 2013
Creating e Wrapper for system verilog code
Hi all, I am try to creating eRM Wrapper for sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification component. but i need how to interfere this both Verification component. if any body have an Idea about this...
Posted to
Functional Verification
(Forum)
by
Selvavinayak
on Wed, Mar 27 2013
Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 27 2013
Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013
Coinciding with the first day of CDNLive! Silicon Valley, our Udacity MOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and we are happy this day has finally come. Last week we gave you a sneak preview of the interactivity...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Mar 12 2013
DVCon 2013: Functional Verification Is EDA’s “Killer App”
With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from this informative event: DVCon 2013 was a one stop...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Sun, Mar 10 2013
DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?
If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog , did just that with a DVCon 2013 panel, where he asked panelists what will be required to reach 1 million new semiconductor design starts per...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Mar 1 2013
Securing Invisible Things … or “Why Denial Works!”
The opening keynote of the Embedded World conference in Germany left me with chills. No, it was not a grand theatrical performance letting me crave for more. It simply scared the bejevies out of me with respect to the safety and security of embedded devices, some of which I use each day. Luckily -- as...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, Feb 27 2013
Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions
The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 27 2013
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