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CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 8 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models
As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 17 2012
High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump Era?
Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis Deployment: Are We Ready?," which can be found here . His conclusion is that we are getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 26 2012
DAC 2012: High-Level Synthesis Tutorial Standing Room Only
Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing SystemC to Layout , led by Michael Bohm of Intel. The first session had over 100 attendees, standing room only: Later sessions each had over 50 attendees. The tutorial featured topics ranging from designing using...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 5 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jan 22 2012
Webinar Seeks to “End the Debate” – e or SystemVerilog?
Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 21 2011
Q&A: After 20 Years, Hierarchical Design and Verification Gets Real
It seems like a simple proposition -- you should be able to design and verify at a high level of abstraction, without re-verifying everything at a low level. But after 20-plus years of discussion in academia and industry, that's still not the case for most design teams. Cadence Fellow Bob Kurshan...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, May 1 2011
Five Modeling Abstraction Levels Clarify Meaning of “ESL”
Since I've complained in the past that electronic system level (ESL) means little more than "anything above RTL," anything that can provide more insight into just what is above RTL is welcome. I have found some clarification through five levels of modeling abstraction described in TLM-Driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 30 2010
What Cadence and TSMC Learned from ESL Reference Flow 11
In what may be a defining moment for electronic system level (ESL) design, TSMC this June announced Reference Flow 11.0 , which extends TSMC's Open Innovation Platform to system-level design. Why was the flow developed, what was Cadence's role , and what was learned in the development of this...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 27 2010
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