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verification,EDA360,UVM

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 9 2012
Secrets of the (Verification) Alliance

In a recent post , I discussed the need for cross-vendor cooperation in EDA, especially in my world of functional verification. It takes a blend of innovative technologies and methodologies to verify a modern system-on-chip (SoC). Customers also need training, consulting services to fill short-term needs...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Nov 29 2011
DVCon? Are You Sure It's Not UVMCon or MSVCon?

As I write this, I've just returned from the most important conference and tradeshow of the year for functional verification: DVCon in San Jose. The "DV" officially stands for "Design and Verification" but most people think that it means "Design Verification" since the...

Posted to Functional Verification (Weblog) by tomacadence on Fri, Mar 4 2011
UVM - The Progress Continues With Reference Flow

As 2010 ends and 2011 begins, the most important thing that came out of the Universal Verification Methodology (UVM) was the UVM Reference Flow. We are thrilled with the results coming from this community contribution. With over 1,000 downloads already, it is clear that UVM has moved into the mainstream...

Posted to Functional Verification (Weblog) by IEM JB on Fri, Dec 17 2010
CDNLive! Silicon Valley 2010 in the Rear-View Mirror

Well, we all survived another very busy CDNLive! event last week. Since I posted a preview beforehand I would be remiss if I didn't let you know what happened. The bottom line is that this was a really good show, with more than forty talks covering a wide range of EDA and EDA360 topics. The majority...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Nov 2 2010
24 Free Webinars Explore Silicon Realization Topics

Twenty-four is a big number when it comes to the number of one-hour webinars planned for a single two-month period. Yet that's what Cadence is planning in a new series of Silicon Realization webinars, slated to begin Oct. 20 and run through Dec. 10. Over the past several months Cadence has offered...

Posted to Industry Insights (Weblog) by rgoering on Fri, Oct 15 2010
Video: Report From The Front Lines Of The Silicon Valley Electronics Industry With AE Darrow Chu

Lately the tone of the trade press and blogs about the Silicon Valley electronics industry has been largely positive. For a variety of reasons this is a good thing, but my natural skepticism compelled me to "field check" this data with a high quality primary source: one of our crack Application...

Posted to Functional Verification (Weblog) by jvh3 on Mon, Sep 27 2010

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verification,EDA360,UVM

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

Secrets of the (Verification) Alliance

DVCon? Are You Sure It's Not UVMCon or MSVCon?

UVM - The Progress Continues With Reference Flow

CDNLive! Silicon Valley 2010 in the Rear-View Mirror

24 Free Webinars Explore Silicon Realization Topics

Video: Report From The Front Lines Of The Silicon Valley Electronics Industry With AE Darrow Chu