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verification,Cadence,Simulation
Accellera
Adam Sherer
Advanced Profiler
ARM
aspect-orieinted programming
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Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques
You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 8 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 7 2012
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