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The Role of Coverage in Formal Verification, Part 2 Continued…
Recall that three main questions need to be answered to attain coverage in formal verification: Part 1 of this series addressed, "How good are my formal constraints?" In Part 2 we showed debugging of over-constraining with help of examples, addressing the question, "How good is my verification...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Jan 27 2011
Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification (ABV), Today and Tomorrow
Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who directs the company's R&D efforts in formal verification -- spoke with Industry Insights columnist Richard Goering . In a wide ranging interview they discussed formal verification usage trends, benefits, roadblocks...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Sun, Jan 23 2011
The Role of Coverage in Formal Verification, Part 1 of 3
As outlined in a prior post , new advances in formal and multi-engine technology (like Incisive Enterprise Verifier or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Jan 3 2011
"ClubT" Newsletter Issue #3 Just Posted
Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter is now posted here , and once again there is exciting news around e , Specman, and Verification. Articles include: * Have you heard of OVM e ? * Incisive 8.2 Technology Update * Verification IP Portfolio E-x-p-a...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jan 27 2009
A Look Back On 2008 (Before Hazarding Predictions for 2009)
Before I dare take a stab at adding to the many predictions already made for 2009 (like those in EE Times and SCD Source ), allow me to share with you some of the main verification technology-specific observations that the "Trailblazer" team saw in 2008: 1 billion logic gate chip roadmaps As...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Jan 7 2009
Heads-up: Formal + Productivity Flow Technical Webinar Coming Up On Nov 12th
Heads-up: there is a free technical webinar next Wednesday 11/12 that goes deeper into the topic of combining formal verification with Cadence's planning & management technology to dramatically improve the throughput of proving assertions, and bug hunting in general. In a phrase, this is a new...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Nov 5 2008
Report from last week's "ClubT" events; preview of next week
As promised, here are some photos last week events, with embedded color commentary. NOTE: there are two additional events next week that will be featuring none other than fellow blogger and Cadence Distinguished Engineer Mike Stellfox: Kista, Sweden on Monday October 6 Bristol, UK on Wednesday October...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Oct 1 2008
In the EU next week for "ClubT" verification events
I'll be in the EU next week supporting "ClubT" events focused on advanced verification, with previews of new developments in the "Trailblazer" program. If you are based in the EU and are active in verification in any way, chances are you have already received a direct invitation...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Fri, Sep 19 2008
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