Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> variation
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
variation
10nm
14nm
20 nm
20nm
20nm webinar
20nm whitepaper
28nm
45nm
ADE
ADE XL
ADE-GXL
ADE-XL
advanced node
analog
Analog Design Environment
Analog Artist
Analog Design Environment
Analog simulation
ARM
ARM Techcon
Cadence
ccopt
change
Chong
clock concurrent optimization
clock tree synthesis
CMP
colorization
corner analysis
Cortex-A15
CTS
Custom 2.0
custom design
Custom IC
Custom IC Design
custom/analog
Dark Silicon
dependency management
Desharnais
design rules
DFM
digital
Digital Implementation
Docea
Double Patterning
DRC
EDA
EDA standards
EDI
EE Times
electromigration
EM
Encounter
EUV
extraction
fin pitches
FinFET
FinFets
FlexModels
giga hertz
giga scale
GigaFlex
giga-scale
Hogan
IBM
Industry Insights
LDE
lithography
sensitivity analysis
Si2
sidewall image transfer
signoff
Silicon Integration Initiative
silicon photonics
silicon realization
Simulation
SIT
SoC
SoC Integration
SSTA
standard cells
Standards
static timing
Statistical
statistical analysis
statistical corners
statistical models
Steve Schulz
stitching
variability
Variability Aware Design
variation analysis
variation-aware
via rules
Virtuoso
Virtuoso Analog Design Environment
Virtuoso IC6.1.5
webinar:
Whiteman
Yeric
Archived Webinar: Variation-Aware Analysis for Advanced Node Design
Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Nov 11 2012
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Nov 2 2012
Si2: Jim Hogan Predicts “Custom 2.0” IC Design Retooling
A re we heading for a major retooling in custom IC design? EDA veteran Jim Hogan thinks so, and in a keynote speech at the Silicon Integration Initiative ( Si2 ) Conference Oct. 9, 2012, he argued that the consumer electronics marketplace will drive a new era he calls "Custom 2.0." The Si2...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 11 2012
Whitepaper: 20nm is More Than Just Double Patterning
Probably the most discussed challenge of the 20nm process node is double patterning, which uses extra masks in order to get lithography equipment to print correctly. That is, indeed, a major change that has impacts throughout the design flow. But as a newly published Cadence whitepaper points out, double...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 9 2012
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions
At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 2 2012
Things You Didn't Know About Virtuoso: Change is Here to Stay
Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis. After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Apr 5 2012
28 nm IC Design: The Devil Is In The Details
Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die...
Posted to
Digital Implementation
(Weblog)
by
Nora
on Mon, Mar 14 2011
Re: What's cadence's answer to SNPS PrimeTime VX
[quote user="Aidans"] SNPS launch its SSTA tools, PrimeTime VX, Is there a similiar product line in Cadence ? [/quote] Hi Aidans , Thank you for your question. Cadence's SSTA technology is available in the Encounter Timing System product for analysis and is the only solution which is integrated...
Posted to
Digital Implementation
(Forum)
by
mikeNaustin
on Tue, Dec 9 2008
Page 1 of 1 (8 items)