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Virtuoso IC6.1.5
Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support
February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out. You'll find databases with detailed instructions, documentation and videos on many tools, features and flows. They've become...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Mon, Mar 18 2013
Virtuoso Advanced Node: Analyzing Layouts Before They’re Done
One paradox of advanced node (28nm and below) custom IC design is that the layout "context" -what is placed near to a device - can change the performance of a device by as much as 30%. Thus, designers must be able to predict layout-dependent effects (LDE) before the final layout is completed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 28 2013
Margins are Costly - Don't Let Them Grow Out of Control!
Last week, Professor Jan Rabaey of the University of California at Berkeley gave a great keynote at Cadence's Low Power Technology Summit that called for changes to the conventional solutions for power reduction. One of the points he made was that today's designs are over-designed and over-constrained...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Oct 24 2012
20 Questions on 20nm – And a New Resource for Advanced Node Design
If you're currently doing or contemplating IC design at 28nm and below, you no doubt have some questions. One place to get a lot of them answered is an Advanced Node microsite newly launched by Cadence for both digital and custom/analog designers. And one interesting (and new) document you'll...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 26 2012
Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs
There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 14 2012
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions
At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 2 2012
EDA Symposium: Users Cite 3D-IC Design Tool Needs
What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium ( EDPS ) April 6, 2012 in Monterey...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 9 2012
Things You Didn't Know About Virtuoso: Change is Here to Stay
Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis. After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Apr 5 2012
ISQED Keynote: 20nm From a Custom/Analog Perspective
Most of the discussions about the upcoming 20nm process node have focused on digital design. Not so at the International Symposium on Quality of Electronic Design ( ISQED 2012 ) March 20, where Tom Beckley, senior vice president of R&D for Custom IC and Signoff in the Silicon Realization group at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 21 2012
Customer, Partner DFM Concerns Spur New Methodologies
Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 7 2012
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