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uvm,e language

DVCon 2013: Engineers Question EDA Standards Leaders at Accellera “Town Hall” Meeting

Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes . A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by...

Posted to Industry Insights (Weblog) by rgoering on Mon, Feb 25 2013
Cadence Partner Udacity Brings Higher Education to the World

On-line education pioneer Udacity is partnering with Cadence to offer an upcoming free class in functional hardware verification - but Udacity's overall mission is quite a bit broader than that. Says David Evans, vice president of education at Udacity (right): "Our mission is to make high-quality...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 26 2012
UVM e vr_ad -- Specman Read/Write Register Enhancements

If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to 1. Extend a vr_ad_sequence 2. Add a field of the type of the register you want to access 3. In the body() , call the read/write_reg For example...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Nov 23 2012
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 9 2012
UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation. Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
What Does it Take to Migrate from e to UVMe?

So you are developing your verification environment in e , and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
UVM Testflow Phase Debugging- Identifying Blocking Activities

UVM Testflow debugging capabilities have been recently enhanced through the addition of more information to the output of the show domain command. In this post, we demonstrate how this information can be used to answer such questions as 1. What domains are in the environment? What units do they contain...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Jul 16 2012
The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...

Posted to Functional Verification (Weblog) by PeteHeller on Tue, May 15 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012

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uvm,e language

DVCon 2013: Engineers Question EDA Standards Leaders at Accellera “Town Hall” Meeting

Cadence Partner Udacity Brings Higher Education to the World

UVM e vr_ad -- Specman Read/Write Register Enhancements

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

UVM Testflow Phases, Reset and Sequences

What Does it Take to Migrate from e to UVMe?

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

UVM Testflow Phase Debugging- Identifying Blocking Activities

The Facts: Why Accelerated VIP Is Needed for SoC Verification

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification