Home > Community > Tags > uvm
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

uvm

  • Why The UVM Is Ready For Production Use Today - Part 1

    As I mentioned in my DAC report , I spent the largest percentage of my time at the OVM-UVM booth, educating attendees on the status of the Universal Verification Methodology (UVM) and answering their questions. Many people had heard about the UVM, although some were unclear on its relation to the Open...
    Posted to Functional Verification (Weblog) by tomacadence on Tue, Jun 29 2010
  • DAC Perspective One Week Later

    DAC in Anaheim last week was as busy as always, perhaps more so, and of course I arrived back in San Jose to a mountain of work set aside during the show and the run-up to it. But I have dug myself out enough to look back at DAC and make a few observations. First of all, I know that overall attendance...
    Posted to Functional Verification (Weblog) by tomacadence on Fri, Jun 25 2010
  • DAC Cabbie Taught Me All I Need to Know About Verification

    Confidence from competence. Measurement through metrics. Sell without selling. These are the pearls I learned from my cab driver on the way home from DAC. Aside from the core truths they convey, they clearly define the top three verification items I saw at 47th DAC in Anaheim this year. Topping my list...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Jun 21 2010
  • Hit The Road - DAC!

    OK, now that the Design Automation Conference (DAC) seems to be rotating among San Francisco, San Diego, and Anaheim, there's not too much "hitting the road" for us Silicon Valley denizens. We either drive an hour north to SF or fly an hour south to SoCal. This year DAC is in Anaheim, where...
    Posted to Functional Verification (Weblog) by tomacadence on Sun, Jun 13 2010
  • Snapshots From Day 0 of DAC 2010

    Below are some snapshots of some "day 0" events, and last minute DAC preparations. Evidence of growing SystemC tide: it was an amazingly beautiful Sunday here in Anaheim -- perfect beach weather. However, ~50 creators & integrators were hunkered down taking notes at the NASCUG meeting....
    Posted to Functional Verification (Weblog) by jvh3 on Sun, Jun 13 2010
  • Specman, e, and EDA360

    The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 8 2010
  • The Future of OVM, VMM, and UVM

    In my last blog , I took a look back at the history of how we got to the first delivery of UVM. Now, let's take a look forward. Over the past week since UVM was released, and Cadence opened the UVMWorld portal to support the new UVM Community and ecosystem, I have seen a number of customers asking...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 24 2010
  • UVM World Community Site Now Available!

    Yesterday morning, the verification world was buzzing with the first release of the Universal Verification Methodology (UVM) standard library and documentation from Accellera. This represents a major milestone for Accellera as well as for the EDA industry, since it is the first time that all the major...
    Posted to Functional Verification (Weblog) by tomacadence on Tue, May 18 2010
  • UVM - 10 Years in the Making ...

    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
  • Initial Release of the UVM Now Available!

    As Richard Goering just reported , the Accellera VIP Technical Subcommittee (TSC) this morning posted the first release of the Universal Verification Methodology (UVM), tagged "1.0 Early Adopter" since there is a bit of new technology beyond the OVM 2.1.1 baseline. This is great news for the...
    Posted to Functional Verification (Weblog) by tomacadence on Mon, May 17 2010
Page 17 of 19 (187 items) « First ... < Previous 15 16 17 18 19 Next >