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uvm,SystemC

DVCon 2013 Preview – Learn from Other Design and Verification Engineers

The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 24 2013
Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to TLM

One of the main benefits of moving the design entry point up in abstraction from RTL to SystemC/TLM is faster verification turnaround. Higher abstraction contains much fewer details, so simulation at that level runs faster and debug is much more productive. But in order to reduce overall verification...

Posted to System Design and Verification (Weblog) by Jack Erickson on Wed, Nov 28 2012
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
Free UVM Tutorial Boosts IC Functional Verification Skills

Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 12 2012
The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...

Posted to Functional Verification (Weblog) by PeteHeller on Tue, May 15 2012
DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards

How will EDA standards move forward, now that the Accellera standards organization and the Open SystemC Initiative (OSCI) have merged into the Accellera Systems Initiative ? That was the topic of a "town hall" forum lunch at the DVCon conference Feb. 27, 2012. No presentations here, no speeches...

Posted to Industry Insights (Weblog) by rgoering on Mon, Feb 27 2012
“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language

The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 17 2012
2011 EDA Standards Update and 2012 Forecast

As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 21 2011
Accellera-OSCI Union Completed – What It Means for EDA Standards

Two prominent EDA industry standards organizations -- Accellera and the Open SystemC Initiative ( OSCI ) - announced today (Dec. 5) the completion of their merger under the name "Accellera Systems Initiative." The stage is now set for a unified EDA standards effort that cuts across multiple...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 5 2011
Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request. In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20. Cadence pioneered...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Oct 18 2011

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uvm,SystemC

DVCon 2013 Preview – Learn from Other Design and Verification Engineers

Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to TLM

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Free UVM Tutorial Boosts IC Functional Verification Skills

The Facts: Why Accelerated VIP Is Needed for SoC Verification

DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards

“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language

2011 EDA Standards Update and 2012 Forecast

Accellera-OSCI Union Completed – What It Means for EDA Standards

Come See How to Connect SystemVerilog and SystemC Using UVM