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testbench

Software-Driven Verification – a Hot Topic for 2013?

Many engineers today use C language software running on an embedded processor model to build testbenches for hardware verification. This "software-driven verification" technique is an ad-hoc methodology that often uses home-grown tools. But it's something you may hear more about in 2013...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 3 2013
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 9 2012
Free UVM Tutorial Boosts IC Functional Verification Skills

Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 12 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help? Knowing that this customer compiles their e code, and...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Aug 15 2012
User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation

When Intel engineers were asked to verify one of the company's largest Many Integrated Core (MIC) designs, they faced a quandary. On one hand, they wanted the visibility and debug features provided by their Specman e language simulation environment. But they also wanted the much faster speeds provided...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 2 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos . The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 23 2012
UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action . It is a must see for the cowbell aficionado. Coincidentally...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 16 2012
My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647) Initially I thought: "What is the fuss all about?" While exploring the language during the development of the cowbell videos , it hit me -- I started to recognize the power of Aspect Oriented...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Jul 10 2012

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testbench

Software-Driven Verification – a Hot Topic for 2013?

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

Free UVM Tutorial Boosts IC Functional Verification Skills

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)