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test

Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 22 2013
The Case for the Tiny Testcase

I often joke with customers that, although I realize they have to work on large designs, I do my best work on designs with just 2 or 3 instances. That's because I'm often trying to replicate an issue they've observed on their design and I'm attempting to reproduce that behavior in a smaller...

Posted to Digital Implementation (Weblog) by BobD on Fri, Nov 16 2012
A New Information Resource for 3D-IC TSV Design

A new solutions page on Cadence.com provides a great deal of information about 3D-ICs with through-silicon vias (TSVs). In addition to a description of the Cadence 3D-IC design, test, and semiconductor IP solutions, it includes press releases, blog posts, whitepapers, articles, and an archived webinar...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 16 2012
Digital Logic in Analog Block – How Will You Test It?

Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 10 2012
Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Jul 24 2012
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 14 2012
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction except for some high-end CPU server and networking...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 10 2012
Trying to Make Sense of the Chaos – Impressions from Design West 2012

Walking the show floor of "Design West," the show formerly known as "Embedded Systems Conference," I was as confused as ever. This was the most diverse exhibition I have ever been to. The 222 exhibitors varied from vendors offering system-level modeling with UML/SysML, lifecycle tracking...

Posted to System Design and Verification (Weblog) by fschirrmeister on Tue, Apr 3 2012
Design for Test (DFT) – New Challenges at Advanced Process Nodes

Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. To...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 15 2011
How Imec and Cadence “Wrapped Up” 3D-IC Test

One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 1 2011

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test

Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

The Case for the Tiny Testcase

A New Information Resource for 3D-IC TSV Design

Digital Logic in Analog Block – How Will You Test It?

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Trying to Make Sense of the Chaos – Impressions from Design West 2012

Design for Test (DFT) – New Challenges at Advanced Process Nodes

How Imec and Cadence “Wrapped Up” 3D-IC Test