Home > Community > Tags > techfile
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

techfile

  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
  • define arrayed contacts in techfile

    The DRC rules require different spacings for two single contacts and an arrayed contacts. For example, when there are only two V1 vias, the spacing is 0.21. If the vias form an 4x4 array, the spacing should be 0.25 instead. In the technology file, we can create symbolic contacts which can be called when...
    Posted to Custom IC SKILL (Forum) by Howel on Wed, May 22 2013
  • how to add a special layer for a custom transistor (pcells) in a techfile

    In a standard techfile provided by Cadence (as an example in cadence_inst/tools.lnx86/dfII/samples/ROD/rodPcells), i can sucessfully creat the mos devices as the pcells. But for some reasons, i need to add another speical layer (its shaper and position should be the same as either nwell in nmos or pwell...
    Posted to Custom IC SKILL (Forum) by fuelectronics on Tue, Apr 16 2013
  • Technology File Modification Issues / Encounter Prevent ViaCell Generation

    We are using the IBM cmrf8sf PDK. We have designed a standard cell library, but we were not able to import this into Abstract Generator because it lacked required metal spacing. To remedy this, we dumped the cmrf8sf techfile, added the required spacings, compiled it and attached to a library copy, and...
    Posted to Digital Implementation (Forum) by bsparkma on Tue, Jul 31 2012
  • diffusion-to-substrate contact (ict file)

    Hi, I converted an ITF file to an ICT file. I encountered to a definiton for diffusion-to-substrate contact. I couldn't find any equivalent keyword to define this in ICT file. I appreciate if anyone help me. Thanks
    Posted to Digital Implementation (Forum) by yazdan on Mon, Oct 17 2011
  • Re: How do I get spacing rules from the techfile tables?

    Hope These may help you ... tfId = techGetTechFile( deGetEditCellView()) techGetSpacingRules(tfId) techGetOrderedSpacingRules(tfId) leGetContactNameArray(tfId) leGetContactDefaultParam(dbOpenCellViewByType(libName cellName viewName)) leGetContactRule(dbOpenCellViewByType(libName cellName viewName)) Best...
    Posted to Custom IC SKILL (Forum) by Prabhu The ICL on Tue, Jun 28 2011
  • how to get FAB pdks

    Greetings! Can anyone guide me how exactly can we (a University IC Design Lab) get a FAB PDK for our projects? Is the NCSU CDK a substitute for the actual FAB PDKs? Can the GDS II file of a project using NCSU CDK sent to the FAB for fabrication? If so, what is the difference between the FAB's PDK...
    Posted to Digital Implementation (Forum) by Mashhood on Wed, Jun 22 2011
  • Confused TechFile & Simulation

    Hello, I designed my own transistor layout by coding a SKILL pcell. The next thing should be a own spectre modle, but the only thing I can do right now is: -create a schematic view for my layout which would include a transistor out of my techfile Normaly I thought I would connect some kind of spectre...
    Posted to Custom IC Design (Forum) by eactor on Thu, May 12 2011
  • RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute

    I am using Cadence Abstract Generator to create abstract cell views for a standard cell library. In the Verify Step, I keep getting the following error: Encounter: (NRDB-158) There is no default via from LAYER MET1 to LAYER MET2 in RULE LEF_DEFAULT. I do not know how or where to define this RULE LEF_DEFAULT...
    Posted to Custom IC Design (Forum) by eklikeroomys on Tue, Mar 15 2011
  • Power Net Extraction Problem in Abstract Generator

    Halo, I am creating abstract cell views for a digital standard cell library using Cadence Abstract Generator.I have the following problem: In the Extract Step, I set the tool up to extract signal and power nets and to create pins on metal 1 so that my abstract view will keep its connectivity. The extract...
    Posted to Custom IC Design (Forum) by eklikeroomys on Mon, Mar 14 2011
Page 1 of 2 (11 items) 1 2 Next >