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Send Yourself A Copy
tcl
"db access"
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Re: Creating Bom variants on a schematic page with multiple instances
The above Tcl command will work on 16.5 release and 16.3 ISR 39 onwards.
Posted to
PCB Design
(Forum)
by
Kuenga606
on Tue, Nov 22 2011
What's Good About Refresh, Copy Project, TCL in SCM? 16.5 Has a Few New Enhancements!
There are several enhancements in the 16.5 System Connectivity Manager ( SCM ) / Allegro System Architect ( ASA ) product that I’ve compiled below that I'm sharing in a brief post this week. Please take advantage of these new 16.5 capabilities. Refresh Option in File Viewer We now have the...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Mon, Nov 7 2011
IPC communication between Python and Cadence
Hi All, I am trying to open a IPC channel between python and cadence. I managed to get one way communication from either to the other, but unable to get two way communication. Please help to point me in the right direction! Thanks in advance, Vijay
Posted to
Custom IC SKILL
(Forum)
by
Vijay Srini
on Tue, Aug 16 2011
How to get screen copies under specific view condition
After Route operation, I take screen copies under specific view conditions, (area, specific layer, specific object, congestion map and so on) It's quite routine work but take time due to the volume I have to care. Can EDI get screen copies automatically under a specific condition? Ex. PhysicalView...
Posted to
Digital Implementation
(Forum)
by
Teru
on Tue, Aug 9 2011
Encounter Puzzler #3 Solution: Renaming a Net Logically
Once again, the Encounter Digital Implementation designer community has stepped up to the challenge. Last week's puzzler -- renaming a net logically in Encounter -- was solved in short order. Let's add J2mh and Sims to the list of Encounter Wizards (along with regular commentator and guest blogger...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Wed, Mar 9 2011
Encounter Puzzler #3: Renaming a Net Logically
The other day a designer E-mailed me: How can we rename a net in Encounter? I followed up to clarify whether the designer wanted to change the net associated with routed wire segments, or wanted to rename a signal net. He clarified that he wanted to change a logical signal net's name. Changing the...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Mon, Feb 28 2011
Guest User Blog: dbShape For All Your Logical Operation Needs
This is a guest post from Jason Gentry at Avago. I hope you enjoy this useful piece he's contributed on using the Encounter Digital Implementation System's dbShape command that debuted in 10.1. I figured it was time for another guest blog, especially since I've been able to play with one...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Wed, Feb 16 2011
RTL compiler inner clock definition
Hi developers! :) I've faced with problem with defining of timing constraint in RTL Compiler. In my design inner clock is generated based on signals from two input pins (xor on two signals actually). How can i tell to RTL Compiler, that this inner signal is a clock? I tried create_generated_clock...
Posted to
Logic Design
(Forum)
by
EvgeniySUAI
on Tue, Dec 14 2010
How to preload a memory in a design using Tcl scripts in NCSIM
I have to verify DMA transfer between two memories present in my design. For example consider there is L1 & L2 cache memories are present in the design. I have transfer 100KB (kilobytes) of data from L1 to L2 by configuring DMA. For the above scenario i have to preload the L1 memory so that simulation...
Posted to
Functional Verification
(Forum)
by
Arrun
on Fri, Dec 10 2010
arguments to tcl file with irun
Hi, I have a requirement where I want to pass arguments to the TCL file used with the irun command for my functional simulation test. A sample example would be irun <options> -input myfile.tcl <tcl_file_arguments> I tried to add arguments to the command line, but the irun interprets the TCL...
Posted to
Functional Verification
(Forum)
by
hrawal
on Wed, Nov 10 2010
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