Home > Community > Tags > systemverilog/OVM e/OVM ML
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

systemverilog,OVM e,OVM ML

  • Analyzing Error Reports When Specman Crashes

    One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: --------- o Rerun the same test with the same seed in...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 17 2012
  • Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

    A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and Richard Goering from Cadence was posted on Cadence.com with the title: " Is e or SystemVerilog Best for Constrained-Random Verification? " This blog post has received much positive feedback from other Specman...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 18 2011
  • "We Want UVM 1.0! When Do We Want it? Now!"

    Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
  • UVM - 10 Years in the Making ...

    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
  • Cadence Exec: Why Cadence is Comitted to e/Specman

    In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering. As...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 16 2010
  • DVCon 2010 For The Specmaniac

    At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
  • OVM Innovation Means Business

    Today, Cadence recognized it's OVM team for their innovative contribution to the Cadence enterprise starting in 2008. Why enterprise? To me, enterprise is the most exciting part because it underscore how the OVM has rallied all of Cadence verification around a common cause which has both polished...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Nov 3 2009
  • OVM Tricks and Treats

    Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions. Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge in these methodology sweets! Callback Mechanism...
    Posted to Functional Verification (Weblog) by Team genIES on Fri, Oct 30 2009
  • Why OVM? John Aynsley of Doulos Has 10 Reasons

    Believe it or not, sometimes a marketing guy just needs to say less. It's true. It does happen. Sometimes we do just get right to the point. Yeah, we do blather on sometimes but ... oops, there I go again. Just listen to John. He has 10 great reasons to adopt the OVM. If video fails to play please...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 22 2009
Page 1 of 2 (11 items) 1 2 Next >