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systemverilog,MDV

  • Specman, e, and EDA360

    The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 8 2010
  • DVCon 2010 For The Specmaniac

    At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
  • A Look Back On 2009 (Before Hazarding Predictions For 2010)

    Before I gaze into a crystal ball and add to the many fine predictions already made for the remaining 11/12ths of 2010 (articles by my colleagues Jack Erickson and Richard Goering are my favorites so far); allow me to review my 2009 predictions against the main verification technology-specific observations...
    Posted to Functional Verification (Weblog) by jvh3 on Thu, Jan 28 2010
  • Scalability Made OVM The Ideal Choice For UVM

    The popularity of OVM that made it the idea choice for Accellera's UVM is rooted in it's uniquely scalable architecture. Today's announcement by Mitsubishi Electric and the OVM Advanced Topics tutorial at DVCon are examples of scalability beyond the common SystemVerilog testbench. For some...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Jan 25 2010
  • Xilinx SoC FPGAs Ideal Fit For OVM and MDV

    Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009). In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Jun 24 2009
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