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systemverilog,IES,OVM e

  • "We Want UVM 1.0! When Do We Want it? Now!"

    Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
  • OVM Tricks and Treats

    Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions. Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge in these methodology sweets! Callback Mechanism...
    Posted to Functional Verification (Weblog) by Team genIES on Fri, Oct 30 2009
  • "ClubT" Newsletter Issue #3 Just Posted

    Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter is now posted here , and once again there is exciting news around e , Specman, and Verification. Articles include: * Have you heard of OVM e ? * Incisive 8.2 Technology Update * Verification IP Portfolio E-x-p-a...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 27 2009
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