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systemverilog,IES,IES-XL

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!

TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration Session: 5T on Thursday, Feb. 28 th from 8:30AM - 12:00PM For more details on the debug tutorial, click here This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most...

Posted to Functional Verification (Weblog) by Karnane on Wed, Feb 20 2013
IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 13 2013
Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...

Posted to Functional Verification (Weblog) by Karnane on Tue, Feb 5 2013
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your engine at any time. The February 23, 2012 webinar...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 22 2012
"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders of the verification engineer. With Amiq's...

Posted to Functional Verification (Weblog) by Team genIES on Fri, Jan 8 2010
Create a Sine Wave Generator Using SystemVerilog

Two capabilities in SystemVerilog allow for the creation of a module that can produce a sine wave as an output: the ability to pass real values through port connections and DPI. Obviously, to produce a sine wave, you need access to the sin function. This is where DPI is handy to add the math functions...

Posted to Functional Verification (Weblog) by tpylant on Tue, Jun 30 2009
Enabling OVM Transaction Debug in SimVision Without Code Changes

Are you tired of putting print statements in your code to do debug? Do you work with designers who just want to use waveforms to debug testbench and design problems? There is a cool feature in the OVM library and Incisive Enterprise Simulator that comes to the rescue. It is the built-in OVM transaction...

Posted to Functional Verification (Weblog) by Team genIES on Thu, Jun 11 2009

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systemverilog,IES,IES-XL

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!

IBM and Cadence Collaboration Improves Verification Productivity

Improve Debug Productivity - SimVision Video Series on YouTube

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Gentlemen, Start Your Simulation Engines

"We Want UVM 1.0! When Do We Want it? Now!"

AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

Create a Sine Wave Generator Using SystemVerilog

Enabling OVM Transaction Debug in SimVision Without Code Changes