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systemverilog modport

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  • SystemVerilog modport question

    Hi All, I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is driven by the master. I would like the interface to split the bus such that one slave is driven by...
    Posted to Functional Verification (Forum) by SCollins on Thu, Sep 13 2012
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