will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > system-level/FPGA
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Panelists: FPGA Tool Opportunity is at the System Level

    FPGA designers in the past got by with free or low-cost tools, and didn't provide much revenue for EDA companies. According to panelists at DesignCon Feb. 1, those days are going fast. A new era of complex FPGAs is opening a tremendous opportunity for new EDA support, especially at the system level...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 2 2011
Page 1 of 1 (2 items)