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system verilog,Specman e TLM ports

  • Creating e Wrapper for system verilog code

    Hi all, I am try to creating eRM Wrapper for sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification component. but i need how to interfere this both Verification component. if any body have an Idea about this...
    Posted to Functional Verification (Forum) by Selvavinayak on Wed, Mar 27 2013
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