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system design and verification

Q&A: What Cadence Has Learned About High Level Synthesis

With the recent release of Cadence C-to-Silicon Compiler, Cadence has joined the rapidly growing high-level synthesis (HLS) marketplace. In this interview Mike "Mac" McNamara, vice president and general manager of the Cadence Systems Software Group, talks about what Cadence has discovered about...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 24 2010
Crises In The Semiconductor Industry

I am on my way to Japan and I have just finished to read an excellent book and in my opinion a "must have" for any marketer and executive in the EDA and the semiconductor industries. The book is called " Chips and Change - How Crisis Reshapes the Semiconductor Industry " by Clair...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Mar 23 2010
Quiet Before The Storm? And What to Expect at DVCon 2010

In the last couple weeks Mentor did an about-face and decided to embrace SystemC ( I told you that would happen! ), and then Synopsys threw down the gauntlet and decided to buy two Virtual Protoyping companies. Supposedly, the word on the street is they are preparing to buy a high-level synthesis company...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Mon, Feb 22 2010
Methodology Is Important But Language Matters - Part 2

In this blog, I would like to discuss the direction in the languages that will be chosen for TLM (or ESL) verification. Transaction-Level Models have been used for long time as simulation models. As we start to use more and more high-level synthesis, the link to design and implementation is becoming...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Feb 9 2010
What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology Adoption?

Cadence is in the vanguard of a movement to a higher level of productivity via the abstraction and automation provided by Transaction Level Modeling (TLM). The industry is motivated to adopt this new methodology by its promise of achieving profitable results through project predictability and system...

Posted to System Design and Verification (Weblog) by Steve Brown on Tue, Feb 2 2010
Methodology Is Important But Language Matters - Part 1

Historical trends in languages Many of us have traveled around the world, and while we can often communicate with local people in our own language, we realize it is best to communicate using the local language. It helps to "break the ice" if you at least try to use some of the local language...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Jan 26 2010
Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 6 2010
Back to Work in 2010

It's back to work in 2010. Thanks for all the great feedback in 2009. I plan to continue to bring readers interesting material about System Design and Verification in 2010. When I got back to work this week I fired up an openSUSE 10.2 VMWare image I sometimes use for development. The boot menu is...

Posted to System Design and Verification (Weblog) by jasona on Wed, Jan 6 2010
Is The Industry Ready For Mainstream Adoption of Higher Abstraction?

I was recently part of an industry wide interview conducted by Clive "Max" Maxfield of TechBites . Max is trying to uncover the reality behind the apparent trend to move to the high level abstraction of transactions for design and verification. I gave the Cadence point of view that this is...

Posted to System Design and Verification (Weblog) by Steve Brown on Mon, Jan 4 2010
Android System Verification Part 5

In the previous article I introduced the use of Specman for generating sequences of commands to send to the Android emulator. I demonstrated a better way to generate hardware stimulus compared to using the original telnet connection to the Android console. The technique was also better than trying to...

Posted to System Design and Verification (Weblog) by jasona on Tue, Dec 29 2009

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system design and verification

Q&A: What Cadence Has Learned About High Level Synthesis

Crises In The Semiconductor Industry

Quiet Before The Storm? And What to Expect at DVCon 2010

Methodology Is Important But Language Matters - Part 2

What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology Adoption?

Methodology Is Important But Language Matters - Part 1

Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

Back to Work in 2010

Is The Industry Ready For Mainstream Adoption of Higher Abstraction?

Android System Verification Part 5