Home > Community > Tags > system design and verification/ESC
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

system design and verification,ESC

  • C-to-Silicon Does Not Require a Library Characterization

    One of the key strengths of C-to-Silicon Compiler (CtoS) over other ESL Synthesis tools is its ability to directly read industry standards .lib files. By providing this ability an expensive library characterization which is required by other ESL Synthesis tools is avoided. This approach not only avoids...
    Posted to System Design and Verification (Weblog) by TeamESL on Fri, Feb 13 2009
  • ESC Boston: Day 2

    This morning before heading to ESC it dawned on me that the park across the street from my hotel was the Boston Public Garden . Maybe it was the swans on the hotel logo, but the ironic thing is that the only way I knew about this park was by reading the book Make Way for Ducklings to my kids. I previously...
    Posted to System Design and Verification (Weblog) by jasona on Wed, Oct 29 2008
  • Virtualization Taxonomy

    I arrived safe and sound at the Embedded Systems Conference in Boston today. It's been a few years since I have attended ESC, but it all came back to me quickly, and is just as I remember it, a lot of small booths with vendors showing small boards doing something (hopefully something interesting...
    Posted to System Design and Verification (Weblog) by jasona on Tue, Oct 28 2008
Page 1 of 1 (3 items)