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synthesize RC script,synthesis

  • RTL compiler command for retaining design hierarchy

    Hi, Is there a command in RTL compiler which can force the synthesizer to retain original hierarchy of the design, like there is in Xilinx ISE for instance? Thanks.
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • Propagate a clock from .LIB of a block

    Hello all, I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated...
    Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012
  • RTL compiler - synthesis

    I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...
    Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012
  • RTL Compiler synthesis problem, memory ports not mapped!!! Generated memory macrocells unusable!!!

    Hello, I am facing a problem during the synthesis (RTL Compiler) which I cannot solve. Here is the problem: Initial status: 1) I have coded my digital design in VHDL. 2) The code has been simulated successfully. 3) In my digital design I also need SRAM and ROM macrocells. a. So I used the ARTISAN memory...
    Posted to Logic Design (Forum) by albares on Wed, Jun 30 2010
  • Need help with VHDL libraries in RTL Compiler

    I have an VHDL file that I want to synthesize that starts like this: library ieee; use ieee.std_logic_1164.all; library grlib;(this is a library I define) use.grlib.amba.all; ... when I synthesize with RTL Compiler, it will give me an error like this: "use.grlib.amba.all", no such primary unit...
    Posted to Logic Design (Forum) by yqzhang on Wed, Dec 16 2009
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