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synthesis,rtl compiler

Videos, Presentations Highlight Front-End IC Design Methodologies

Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations and videos from most of the sessions are...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 9 2013
Virtual Clock and Synthesize :)

Hi everyone, I have couple of doubts. Please help me out. 1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for...

Posted to Digital Implementation (Forum) by Ram S on Sat, Mar 16 2013
Re: gray code

Hi gh-, RTL Compiler has no support to control FSM coding style. I vaguely remember even Synplify had a pragma for this (binary, one-hot, gray or Johnson coding). I have done an experiment: Synthesized 9-bit binary counter, and then synthesized 9-bit Gray counter (using CW_cntr_gray) using following...

Posted to Digital Implementation (Forum) by Sporadic Crash on Mon, Oct 29 2012
Re: gray code

I am interested in Gray coding with RTL Compiler. In the tool following synthetic operators are used: BIN2GRAY_STD_LOGIC_OP, GRAY2BIN_STD_LOGIC_OP, INC_GRAY_STD_LOGIC_OP Additionally, following ChipWare components are related to Gray codes. CW_inc_gray, CW_gray2bin, CW_cntr_gray, CW_bin2gray There is...

Posted to Digital Implementation (Forum) by Sporadic Crash on Wed, Oct 24 2012
Digital Logic in Analog Block – How Will You Test It?

Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 10 2012
Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler

Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for RTL Compiler. Before attempting to run synthesis...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Aug 7 2012
Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Jul 24 2012
Propagate a clock from .LIB of a block

Hello all, I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated...

Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012
The Technology Behind Encounter 11.1 – Physical Aware Front End Design

In my last blog post I discussed new optimization and modeling technology in the Encounter 11.1 release, announced by Cadence March 5. While that blog post focused on physical IC ("back end") design, the new release also brings more "physical awareness" to front-end design, and that's...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 6 2012
TLU support for RC?

Hi, is there a possibility in Cadence RC to use TLU or TLU+ data for synthesis? Alex'

Posted to Logic Design (Forum) by Alex Kli on Wed, Feb 8 2012

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synthesis,rtl compiler

Videos, Presentations Highlight Front-End IC Design Methodologies

Virtual Clock and Synthesize :)

Re: gray code

Re: gray code

Digital Logic in Analog Block – How Will You Test It?

Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

Propagate a clock from .LIB of a block

The Technology Behind Encounter 11.1 – Physical Aware Front End Design

TLU support for RC?