Home > Community > Tags > synthesis
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • The Science of Synthesis

    I am passionate about synthesis. Almost 20 years ago I began using Synopsys "Logic Compiler" to do combinational synthesis and optimization from Verilog RTL. At that time it did not support sequential constructs so Flip-Flops had to be manually instantiated in the netlist. Synthesis has matured...
    Posted to Logic Design (Weblog) by Jason Ware on Mon, Dec 8 2008
  • Leveraging Silicon Virtual Prototyping Technology in Synthesis

    How many times has this happened to you? The wireload model based timing engine in your synthesis tool indicates that you have finally closed the timing on your design. You can now hand the design off to the back end implementation engineer and focus on your other tasks. A week or two go by and you get...
    Posted to Logic Design (Weblog) by mrardon on Mon, Nov 17 2008
  • How Do You Synthesize Big Chips?

    One of the advantages of RTL Compiler’s unique global synthesis approach is that the runtime scales linearly with design size. So it is theoretically possible to synthesize any size design top-down on a 64-bit machine. While that would get you the best results, it’s often not practical in...
    Posted to Logic Design (Weblog) by Jack Erickson on Wed, Nov 5 2008
  • setenv command in RTL Compiler

    Hello all, I have a problem with RTL compiler shell. When I use RC in text mode (rc) and type 'setenv' command in it I get message that command not exist. But if I start RC in gui mode (rc -gui) and type the same command - everything is ok. Could anyone explain such behavior and how to use 'setenv'...
    Posted to Logic Design (Forum) by dkos on Wed, Nov 5 2008
  • Why Should I Use a Floorplan for Physical Prediction and Synthesis?

    It goes without saying that performing logical synthesis without timing or power constraints is of limited value at best. The netlist that is painstakingly crafted by a synthesis tool is very much tied to a particular set of constraints. Cell function and sizes have been selected to meet the timing targets...
    Posted to Logic Design (Weblog) by mrardon on Tue, Nov 4 2008
Page 8 of 8 (75 items) « First ... < Previous 4 5 6 7 8