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  • Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical

    By Ankush Sood Principal Product Engineer Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save costs), designs are getting more congested. The normal...
    Posted to Logic Design (Weblog) by Team FED on Tue, Aug 11 2009
  • DesignWare and AmbitWare Demystified - Why and When to Avoid?

    By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware...
    Posted to Logic Design (Weblog) by Team FED on Fri, Jul 24 2009
  • How to Pick a Synthesis Tool - The Right One for You - Part 2

    By Kenneth Chang, Core Comp AE, Team FED . In my previous blog , I had written about how "Synthesis matters." Snippet below. <snip> I had a boss that once said that all synthesis tools are same. This guy knew his stuff, been in the industry forever. He said "synthesizing with Tool...
    Posted to Logic Design (Weblog) by Team FED on Tue, Jul 7 2009
  • Of Rights & Wrongs: The Bottom-up vs. Top-down Methododology Debate

    By Diego Hammerschlag Sr. Technical Leader Team FED The top-down vs. bottom-up methodology decision is one that design engineers should not take lightly. It carries ramifications throughout the hole flow and can certainly make or break a project if not careful. Such methodology decision can impact: Quality...
    Posted to Logic Design (Weblog) by Team FED on Mon, Jun 22 2009
  • New White Paper: Routing Congestion De-Mystified

    Even though routing congestion sounds like a physical design problem, it can cause chip projects to miss schedules, miss performance targets, or result in a larger die size. These are problems that are shared across the project, so if you want to control the success of your chip design project, it is...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Jun 16 2009
  • Don't Let Power Kill Your Project - What % LVT Should I Use?

    By Diego Hammerschlag Sr. Technical Leader Team FED A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can...
    Posted to Logic Design (Weblog) by Team FED on Wed, May 13 2009
  • Overwriting messages warning in RC

    Hi all, I am getting a whole bunch of these warnings while running RC. Warning : Overwriting messages. Specify a different ID or group to avoid overwriting the existing message. [MESG-2] : Overwriting existing message CLP-206 Can anyone let me know what are these warnings regarding. Thanks.
    Posted to Logic Design (Forum) by shift on Tue, Apr 21 2009
  • The Dangers of Excessive Guard Banding

    By Matt Rardon Synthesis Solutions I want to take a couple of minutes to talk about guard banding of constraints in logic synthesis. This approach was initially conceived to add a little bit of padding to the design to account for inaccuracies in synthesis modeling techniques and to provide some wiggle...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 16 2009
  • Is ESL changing EDA? Absolutely!

    Geoffrey James's recent article provides a succinct description of several important trends that are driving customers towards system level design and verification. He makes several points about shifts in technology and methodology, and the fact that the RTL remains the golden source even for today's...
    Posted to System Design and Verification (Weblog) by Steve Brown on Wed, Apr 1 2009
  • Where Oh Where is "number_of_routing_layers"?

    OK, I'll just do " set_attribute number_of_routing_layers 6 "... Error : The attribute is read-only. [TUI-26] [set_attribute] : attribute: 'number_of_routing_layers', object type: 'root' : Cannot set or reset read-only attributes. Hey, wait a minute! If you are faced with...
    Posted to Logic Design (Weblog) by mrardon on Wed, Mar 18 2009
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