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syntheis LEF cell counts

  • Power Net Extraction Problem in Abstract Generator

    Halo, I am creating abstract cell views for a digital standard cell library using Cadence Abstract Generator.I have the following problem: In the Extract Step, I set the tool up to extract signal and power nets and to create pins on metal 1 so that my abstract view will keep its connectivity. The extract...
    Posted to Custom IC Design (Forum) by eklikeroomys on Mon, Mar 14 2011
  • LEF in synthesis flow

    Hi, In RTL compiler synthesis flow, i have set_attribute interconnect_mode ple / And, i have inlcuded the cap table as well set_attribute cap_table_file {$CAP_TABLE/bst.cap } Do i need to include the LEF library for std cells and io cells as well for correct interconnect delay estimation even after including...
    Posted to Logic Design (Forum) by diablo on Mon, Dec 13 2010
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